Semiconductor transistors, in particular field-effect controlled switching devices such as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) or an Insulated Gate Bipolar Transistor (IGBT), have been used for various applications including but not limited to use as switches in power supplies and power converters, electric cars, air-conditioners, and even stereo systems. Particularly with regard to power devices capable of switching large currents and/or operating at higher voltages, low on-state resistance Ron, high breakdown voltages Ubd, high robustness and/or good softness are often desired.
To achieve low on-state resistance Ron and high breakdown voltages Ubd, charge-compensation semiconductor devices were developed. The compensation principle is based on a mutual compensation of charges in n- and p-doped regions, which are often also referred to as n- and p-doped pillar regions, in the drift zone of a vertical MOSFET.
Typically, the charge-compensation structure formed by p-type and n-type regions is arranged below the actual MOSFET-structure, with its source, body regions and gate regions, and also below the associated MOS-channels that are arranged next to one another in the semiconductor volume of the semiconductor device or interleaved with one another in such a way that, in the off-state, their charges can be mutually depleted and that, in the activated state or on-state, there results an uninterrupted, low-impedance conduction path from a source electrode near the surface to a drain electrode arranged on the back side.
By virtue of the compensation of the p-type and n-type dopings, the doping of the current-carrying region can be significantly increased in the case of compensation components, which results in a significant reduction of the on-state resistance Ron despite the loss of a current-carrying area. The reduction of the on-state resistance Ron of such semiconductor power devices is associated with a reduction of the heat generated by the current in the on-state, so that such semiconductor power devices with charge-compensation structure remain “cool” compared with conventional semiconductor power devices.
As many other power semiconductor devices having an active area (cell area) surrounded by a peripheral area, charge-compensation devices are usually designed as vertically conducting devices. Accordingly, the electric current in the on state flows from the source on the front side to drain at the backside of the chip. The backside is often implemented as a “common-drain”, i.e. as an equipotential surface at drain potential. Implementing also the front side as equipotential surface (at source potential) tends to be unfavorable with respect to leakage current and/or blocking behavior due to high electric fields at the lateral chip boundary surfaces (kerf, edge) during the blocking mode. Therefore, the lateral chip boundary at the front side is typically also kept at or close to drain potential during device operation. Next to the front side, a sufficiently smooth voltage drop from source potential in the active area to drain potential next to the lateral chip boundary is typically achieved by edge-termination structures at or next to the front side in the peripheral area. It is often desired that the blocking capability of the peripheral area including the edge is higher compared to the active area. However, the risk of a breakdown in the peripheral area may, for example due to manufacturing variations, be increased for charge-compensation devices also having charge-compensation structure in the peripheral area.
Accordingly, there is a need to improve semiconductor devices with charge-compensation structures and manufacturing of those semiconductor devices.